1. Field of the Invention
The invention relates to analog to digital conversion and more particularly to an anti-noise successive approximation analog to digital conversion method.
2. Description of Related Art
There are many different analog-to-digital converters (ADCs) available. For example, there are flash ADCs, pipelined ADCs, and successive approximation register (SAR) ADCs. Each of them has respective advantages and they are used depending on applications. The SAR ADCs have benefits of consuming less energy, occupying less space, and more cost effective as compared with the flash ADCs and pipelined ADCs.
Typically, SAR ADC employs a binary search algorithm to obtain digital output codes which match input codes. An analog-to-digital conversion circuit of the SAR ADC may add or subtract a binary voltage based on result of each comparison done by a comparator during the conversion. A difference of input signal and reference voltage will be less than a least significant bit (LSB) after the last bit cycle. But noise from the circuit may distort the conversion.
For increasing the noise reduction capability of an SAR ADC, it is typical to design the SAR ADC to be one with very low noise generation. However, it can greatly increase the manufacturing cost of the circuit as well as large area and high energy consumption. There are several known methods which allow higher noise levels in bit cycles of an SAR ADC. These methods employ an error compensation to allow settling error. However, they do not solve the noise problem completely because several last bit conversions without fault tolerant capability are still subject to noise. As a result, the conversion is still distorted.
Thus, the need for improvement still exists.